The present invention relates to technology for increasing the speed of operation of a semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal. More particularly, the present invention relates to technology effectively used for a semiconductor integrated circuit device that has storage circuit blocks such as DRAM and logic circuit blocks on one semiconductor integrated circuit chip and is configured so that a data transfer within the chip is performed synchronously with a clock signal.
In a conventional logic LSI (large-scale semiconductor integrated circuit) in which a storage circuit and logic circuits are formed on a one semiconductor chip, generally a data transfer within the chip is often performed synchronously with a clock signal. For such LSI, when data is transferred from one function circuit to another, inputted data is properly processed before being stored in an internal storage circuit, or data read from the storage circuit is properly processed before being outputted to the outside of the chip, a circuit to receive the data is configured to latch the data synchronously with the rising edge or falling edge of a clock signal (hereinafter referred to simply as a clock). For this reason, it has been common that time required for a data transfer is an integral multiple of the cycle of the clock.